Update #24 : GPU on FPGA, Timer, documentation and the rest...

So what did happen betwen the last update ?

On the 'human resource' side :

- Two people joined the project since my call for help. One left already. (Don't blame me, I was very nice ;-) )
- KrispySmooth also left. (He wrote the DDR stuff, which I rewrote later but that's a detail)
- MikeJ helped me for the Timer thing. He said that for now, after his fix it should be OK for a first trial.
- ElectronAsh gave me a big hand. (See the following stuff)
- Myself : spent time managing all those human factor things (prepair document, explain how to do things, gather info for the people willing to help), took sometime for myself (finally ended LoU 2, after owning the game from nearly day 1) to take a small distance from dev in real life being quite busy and dev on FPGA/HDL on the top of that.

All this was a bit time costly, but at least relieved me of the dev for a while. I am definitely in lack of vacation.

On the task side :
- So Timer is complete now. (Thanks MikeJ !)
- Spent quite some time to document stuff.
- Rewrote myself the DDR stuff, took a look at it.

- ElectronAsh gave a big push, took the DDR stuff, integrated the GPU as a slave component inside MiSTer, so yeah in a real FPGA, not in simulation anymore.
Now the ARM CPU can see it as a coprocessor, and we can see its VRAM as display using Ascal (the display system of MiSTer). We can also read the DDR memory in C and check what the thing is doing. (In the previous update, I talked about it, but it was not complete)

The FPGA stuff was done before, but the real breakthrough happened in the last 24h.

- Fill Rect command seems to be fully operationnal, including when memory command buffer is saturated too.

- Fixed two bugs in the DDR thing. Write commands to the DDR seems OK for now.
We also found another bug in the GPU command parser : differences in timing between simulation condition and real world made a bug apparent, found it 4 hours ago and it was fixed 2 hours ago.


Conclusion :
So yeah, things are taking shape. Starting to see chip working on real hardware is a nice warm and exciting feeling, like watching a baby starting to walk and talk, and at the same time having the fear that the same baby will crash in the stairs with a bug.

So I guess, I will not do new experimental/dev stuff but probably validate the chip on FPGA for a few sessions. Let's see how it goes...

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